Caches, MMU and PU. More...

#include <stdint.h>

Macros
#define	AP(access, el0Permitted) (access \| (el0Permitted ? 1 : 0))
	Define access permissions. More...

#define	COARSE_DESCRIPTOR(tablePhysicalAddr, domain) ((tablePhysicalAddr & 0xFFFFFC00) \| (domain << 5) \| BIT(4) \| 0x1)
	Define a coarse descriptor. More...

#define	FINE_DESCRIPTOR(tablePhysicalAddr, domain) ((tablePhysicalAddr & 0xFFFFF000) \| (domain << 5) \| BIT(4) \| 0x3)
	Define a fine descriptor. More...

#define	LARGE_DESCRIPTOR(physicalAddr, ap3, ap2, ap1, ap0, cacheable, buffered) ((physicalAddr & 0xFFFF0000) \| (ap3 << 10) \| (ap2 << 8) \| (ap1 << 6) \| (ap0 << 4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x1)
	Define a large (64K) descriptor. More...

#define	MMU_COARSE_ALIGN 0x400
	Alignment for L2 coarse table.

#define	MMU_FINE_ALIGN 0x2000
	Alignment for L2 fine table.

#define	MMU_L1_ALIGN 0x4000
	Alignment for L1 MMU table.

#define	PU_REGION(baseAddress, areaSize, enabled) ((baseAddress & 0xFFFFF000) \| (areaSize << 1) \| (enabled ? 1 : 0))
	Define a PU memory region for the ARM940T. More...

#define	SECTION_DESCRIPTOR(physicalAddr, ap, domain, cacheable, buffered) (((physicalAddr) & 0xFFF00000) \| (ap << 10) \| (domain << 5) \| BIT(4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x2)
	Define a section descriptor. More...

#define	SMALL_DESCRIPTOR(physicalAddr, ap3, ap2, ap1, ap0, cacheable, buffered) ((physicalAddr & 0xFFFFF000) \| (ap3 << 10) \| (ap2 << 8) \| (ap1 << 6) \| (ap0 << 4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x2)
	Define a small (4K) descriptor. More...

#define	TINY_DESCRIPTOR(physicalAddr, ap3, ap2, ap1, ap0, cacheable, buffered) ((physicalAddr & 0xFFFFFC00) \| (ap << 4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x3)
	Define a tiny (1K) descriptor. More...

Enumerations
enum	Access { READ_WRITE = 0x0 , READ_ONLY = 0x2 }
	Access permissions for MMU pages. More...

enum	DomainAccess { NO_ACCESS = 0x0 , CLIENT = 0x1 , MANAGER = 0x3 }
	Access permissions for MMU domains. More...

enum	PUAccess { PU_NO_ACCESS = 0x0 , PU_PRIVILEGED_ONLY = 0x1 , PU_PRIVILEGED_RW_USER_RO = 0x2 , PU_FULL_ACCESS = 0x3 }
	Access permissions for PU memory regions. More...

enum	PUAreaSize
	Protection Unit memory region sizes. More...

Functions
void	cacheCleanD ()
	Clean entire data cache. More...

void	cacheDisableD ()
	Disable data cache. More...

void	cacheDisableI ()
	Disable instruction cache. More...

void	cacheEnableD ()
	Enable data cache. More...

void	cacheEnableI ()
	Enable instruction cache. More...

void	cacheInvalidateD ()
	Invalidate data cache. More...

void	cacheInvalidateDI ()
	Invalidate both data and instruction caches. More...

void	cacheInvalidateI ()
	Invalidate instruction cache. More...

void	mmuCachesInitOn ()
	Enables MMU along with data and instruction caches. More...

void	mmuDisable ()
	Disable the MMU. More...

void	mmuEnable (void *l1Table)
	Enable the MMU. More...

uint32_t *	mmuNewL1Table ()
	Allocates and populates a new L1 MMU table. More...

uint32_t	mmuSetDomainAccess (unsigned int domain, DomainAccess access)
	Configures MMU domain access. More...

void	puCachesInitOn ()
	Enables PU along with data and instruction caches. More...

void	puDisable ()
	Disable the PU. More...

void	puEnable ()
	Enable the PU. More...

void	puSetDRegion (unsigned int region, uint32_t params, PUAccess access, bool cacheable, bool buffered)
	Configure a PU data memory region. More...

void	puSetIRegion (unsigned int region, uint32_t params, PUAccess access, bool cacheable)
	Configure a PU instruction memory region. More...

Macro Definition Documentation

◆ AP

#define AP	(	access,
		el0Permitted
	)	(access \| (el0Permitted ? 1 : 0))

Define access permissions.

Parameters

access	READ_ONLY or READ_WRITE
el0Permitted	Access is permitted when running in a non-privileged mode

See also: Access

◆ COARSE_DESCRIPTOR

#define COARSE_DESCRIPTOR	(	tablePhysicalAddr,
		domain
	)	((tablePhysicalAddr & 0xFFFFFC00) \| (domain << 5) \| BIT(4) \| 0x1)

Define a coarse (256 entries) L1 descriptor for large (64K) or small (4K) pages.

Parameters

tablePhysicalAddr	Physical address of L2 table
domain	Domain for this coarse descriptor (0 - 15)

◆ FINE_DESCRIPTOR

#define FINE_DESCRIPTOR	(	tablePhysicalAddr,
		domain
	)	((tablePhysicalAddr & 0xFFFFF000) \| (domain << 5) \| BIT(4) \| 0x3)

Define a fine (1024 entries) L1 descriptor for large (64K), small (4K) or tiny (1K) pages.

Parameters

tablePhysicalAddr	Physical address of L2 table
domain	Domain for this fine descriptor (0 - 15)

◆ LARGE_DESCRIPTOR

#define LARGE_DESCRIPTOR	(	physicalAddr,
		ap3,
		ap2,
		ap1,
		ap0,
		cacheable,
		buffered
	)	((physicalAddr & 0xFFFF0000) \| (ap3 << 10) \| (ap2 << 8) \| (ap1 << 6) \| (ap0 << 4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x1)

Define a large (64K page) descriptor to go into an L2 table.

Parameters

physicalAddr	64K aligned physical address of page
ap3	Access permissions for fourth 16K subpage
ap2	Access permissions for third 16K subpage
ap1	Access permissions for second 16K subpage
ap0	Access permissions for first 16K subpage
cacheable	Section should be cacheable
buffered	Section should be buffered

See also: AP

◆ PU_REGION

#define PU_REGION	(	baseAddress,
		areaSize,
		enabled
	)	((baseAddress & 0xFFFFF000) \| (areaSize << 1) \| (enabled ? 1 : 0))

Define a PU memory region for the ARM940T.

Note: This does not apply to the ARM920T, where there is a full MMU.

See also: PUAreaSize

◆ SECTION_DESCRIPTOR

#define SECTION_DESCRIPTOR	(	physicalAddr,
		ap,
		domain,
		cacheable,
		buffered
	)	(((physicalAddr) & 0xFFF00000) \| (ap << 10) \| (domain << 5) \| BIT(4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x2)

Define a section L1 descriptor (1MB).

Parameters

physicalAddress	1MB aligned physical address of section
ap	Access permissions
domain	Domain for this section (0 - 15)
cacheable	Section should be cacheable
buffered	Section should be buffered

See also: AP

◆ SMALL_DESCRIPTOR

#define SMALL_DESCRIPTOR	(	physicalAddr,
		ap3,
		ap2,
		ap1,
		ap0,
		cacheable,
		buffered
	)	((physicalAddr & 0xFFFFF000) \| (ap3 << 10) \| (ap2 << 8) \| (ap1 << 6) \| (ap0 << 4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x2)

Define a small (4K page) descriptor to go into an L2 table.

Parameters

physicalAddr	4K aligned physical address of page
ap3	Access permissions for fourth 4K subpage
ap2	Access permissions for third 4K subpage
ap1	Access permissions for second 4K subpage
ap0	Access permissions for first 4K subpage
cacheable	Section should be cacheable
buffered	Section should be buffered

See also: AP

◆ TINY_DESCRIPTOR

#define TINY_DESCRIPTOR	(	physicalAddr,
		ap3,
		ap2,
		ap1,
		ap0,
		cacheable,
		buffered
	)	((physicalAddr & 0xFFFFFC00) \| (ap << 4) \| ((cacheable ? 1 : 0) << 3) \| ((buffered ? 1 : 0) << 2) \| 0x3)

Define a small (1K page) descriptor to go into an L2 table.

Parameters

physicalAddr	4K aligned physical address of page
ap	Access permissions
cacheable	Section should be cacheable
buffered	Section should be buffered

See also: AP

Enumeration Type Documentation

◆ Access

enum Access

Access permissions for MMU pages.

Enumerator
READ_WRITE	Read-write.
READ_ONLY	Read-only.

◆ DomainAccess

enum DomainAccess

Access permissions for MMU domains.

Enumerator
NO_ACCESS	Do not allow any access.
CLIENT	Respect the permission bits in the translation table.
MANAGER	Ignore the permission bits in the translation table.

◆ PUAccess

enum PUAccess

Access permissions for PU memory regions.

Enumerator
PU_NO_ACCESS	No access.
PU_PRIVILEGED_ONLY	Only privileged mode access.
PU_PRIVILEGED_RW_USER_RO	Full access from privileged mode, read-only access from user mode.
PU_FULL_ACCESS	Full access from both privileged and user modes.

◆ PUAreaSize

enum PUAreaSize

Protection Unit memory region sizes.

Function Documentation

◆ cacheCleanD()

void cacheCleanD ( )

Clean entire data cache (i.e. write it back to memory).

◆ cacheDisableD()

void cacheDisableD ( )

Disable data cache.

◆ cacheDisableI()

void cacheDisableI ( )

Disable instruction cache.

◆ cacheEnableD()

void cacheEnableD ( )

Enable the data cache.

Warning: This will also enable the MMU or PU if it is not already enabled! Ensure you have set up the MMU or PU first.

See also: mmuEnable

◆ cacheEnableI()

void cacheEnableI ( )

Enable instruction cache.

◆ cacheInvalidateD()

void cacheInvalidateD ( )

Invalidate data cache.

Warning: This does not write back any dirty data!

◆ cacheInvalidateDI()

void cacheInvalidateDI ( )

Invalidate both data and instruction caches.

Warning: This does not write back any dirty data!

◆ cacheInvalidateI()

void cacheInvalidateI ( )

Invalidate instruction cache.

Warning: This does not write back any dirty data!

◆ mmuCachesInitOn()

void mmuCachesInitOn ( )

Enables MMU along with data and instruction caches. This uses a basic setup as per mmuNewL1Table() which should be sufficient for most use cases.

Note: ARM920T only

Warning: This should only be called after gp2xInit as it allocates memory

See also: mmuNewL1Table

◆ mmuDisable()

void mmuDisable ( )

Disable the MMU.

Note: This will also disable the data cache.; ARM920T only

◆ mmuEnable()

void mmuEnable ( void * l1Table )

Enable the MMU.

Note: ARM920T only

Parameters

l1Table Pointer to 16K aligned L1 translation table

See also: mmuNewL1Table

◆ mmuNewL1Table()

uint32_t * mmuNewL1Table ( )

Allocates and populates a new L1 MMU table. This will by default enable caching and buffering for the first 64M of the address space (i.e. RAM) using 1M section descriptors set to domain 0.

Note: ARM920T only

Warning: This should only be called after gp2xInit as it allocates memory

Returns: A pointer to a correctly aligned L1 MMU table

◆ mmuSetDomainAccess()

uint32_t mmuSetDomainAccess	(	unsigned int	domain,
		DomainAccess	access
	)

Configures MMU domain access.

Note: ARM920T only

Parameters

domain	Domain to configure (0 - 15)
access	Access permissions to assign to domain

Returns: State of Domain Access Control Register after the change

◆ puCachesInitOn()

void puCachesInitOn ( )

Enables MMU along with data and instruction caches. This uses a basic setup where all RAM is cached and buffered, which should be sufficient for most use cases.

Note: ARM940T only

◆ puDisable()

void puDisable ( )

Disable the PU.

Note: ARM940T only; This will also disable the data cache.

◆ puEnable()

void puEnable ( )

Enable the PU.

Note: You must have configured a region before calling this.; ARM940T only

See also: puSetDRegion; puSetIRegion

◆ puSetDRegion()

void puSetDRegion	(	unsigned int	region,
		uint32_t	params,
		PUAccess	access,
		bool	cacheable,
		bool	buffered
	)

Configure a PU data memory region.

Note: ARM940T only

Parameters

region	Region to figure (0 - 7)
params	Basic region params (defined using PU_REGION)
access	Access permissions for region
cacheable	Whether region is cacheable
buffered	Whether region is buffered

See also: PU_REGION

◆ puSetIRegion()

void puSetIRegion	(	unsigned int	region,
		uint32_t	params,
		PUAccess	access,
		bool	cacheable
	)

Configure a PU instruction memory region.

Note: The instruction cache is not bufferable.; ARM940T only

Parameters

region	Region to figure (0 - 7)
params	Basic region params (defined using PU_REGION)
access	Access permissions for region
cacheable	Whether region is cacheable

See also: PU_REGION

Macros

Enumerations

Functions

Macro Definition Documentation

◆ AP

◆ COARSE_DESCRIPTOR

◆ FINE_DESCRIPTOR

◆ LARGE_DESCRIPTOR

◆ PU_REGION

◆ SECTION_DESCRIPTOR

◆ SMALL_DESCRIPTOR

◆ TINY_DESCRIPTOR

Enumeration Type Documentation

◆ Access

◆ DomainAccess

◆ PUAccess

◆ PUAreaSize

Function Documentation

◆ cacheCleanD()

◆ cacheDisableD()

◆ cacheDisableI()

◆ cacheEnableD()

◆ cacheEnableI()

◆ cacheInvalidateD()

◆ cacheInvalidateDI()

◆ cacheInvalidateI()

◆ mmuCachesInitOn()

◆ mmuDisable()

◆ mmuEnable()

◆ mmuNewL1Table()

◆ mmuSetDomainAccess()

◆ puCachesInitOn()

◆ puDisable()

◆ puEnable()

◆ puSetDRegion()

◆ puSetIRegion()